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1995 data sheet 120-/128-output tft-lcd gate driver document no. s11041ej1v0ds00 (1st edition) (previous no. ip-3677) date published december 1995 p printed in japan mos integrated circuit m pd16650 the m pd16650 is a tft-lcd gate driver. provided with a level shift circuit at the logic input, this chip can output a high gate scan voltage for a cmos-level input. the m pd16650 has an output change-over function for switching from the 120-output mode to the 128-output mode, and vice versa, thereby supporting the vga, svga, and xga panels. its output enable function (oe) enables installing the driver on either side. features ? output with high dielectric strength (on/off range: v dd - v ee1 = 40 v max .) ? built-in shift direction change-over function ? shiftable negative supply voltage (v ee1 ) level (shift range: |v ee1 - v ee2 | = 10 v) ? two acceptable cmos input levels (3.3 and 5 v) ? output enable function ? mc-selectable output count (mc = high: 120-output mode) (mc = low : 128-output mode) ? slim tcp ordering information part number package m pd16650n- tcp (tab package) m pd16650n- standard tcp (ol pitch = 220 m m) remark when ordering, the customer can specify the external form of the tcp. call one of our sales representatives for more information.
m pd16650 2 block diagram 128-bit shift register ls ls ls ls ls ls v cha r/l x stvr mc oe stvl v ee1 x 1 x 2 x 127 x 128 f remark ls (level shifter): interfaces the 5 v cmos level with the v dd -v ee2 level.
m pd16650 3 pin connection diagram ( m pd16650n- ) ( copper foil side) these pins are ineffective in the 120-output mode. v dd v cha v ee2 stvl oe x r/l v cc mc v ss stvr v ee1 v ee2 x 128 x 127 x 126 x 70 x 69 x 68 x 67 x 66 x 65 x 64 x 63 x 62 x 61 x 59 x 3 x 2 x 1 x 60 f caution the v cha pin should be connected to the v dd or v ee2 pin on the tcp. (this method eliminates the necessity to provide the v cha input pin on the tcp, resulting in a reduction in the number of required input pins.)
m pd16650 4 pin description pin symbol pin name description of function driver output output count change-over input logic voltage change-over input start pulse input/output shift direction change-over input shift clock input output enable input driver positive supply volt- age reference voltage ground driver negative supply volt- age driver negative supply volt- age x 1 to x 128 mc v cha stvr stvl r/l f x oe v dd v cc v ss v ee1 v ee2 output scan signals to drive the tft-lcd gate electrodes. the output changes when the shift clock f x rises. the amplitude of the driver output is v dd - v ee1 . see the timing charts shown later for details of how to switch between the 120- output mode and 128-output mode. receives a signal that changes the number of outputs. for the 120-output mode, this pin must be supplied with a high level (v cc ). for the 128-output mode, it must be supplied with a low level (v ss or v ee2 ). must be supplied with the v ee2 level when the logic supply voltage is 3.3 v, and with the v dd level when the logic supply voltage is 5.0 v. receives an input to the internal shift register. the input data is loaded on the shift register at the positive-going edge of the shift clock f x . the scan signals are output from x 1 to x 128 . the input/output level is the cmos level. outputs a start pulse to the next stage if a cascade connection is used. in the 120-output mode, the start pulse is output at the negative-going edge of the 120th shift clock f x pulse, and cleared at the negative-going edge of the 121st pulse. in the 128-output mode, the start pulse is output at the negative-going edge of the 128th shift clock f x pulse, and cleared at the negative-going edge of the 129th pulse. r/l = high (for shift right): stvr ? x 1 ? x 128 ? stvl r/l = low (for shift left) : stvl ? x 128 ? x 1 ? stvr receives a shift clock pulse for the internal shift register. a shift occurs at the positive-going edge of the shift clock pulse. when this pin is at a high level, the driver output is fixed at a low level. the shift register is not cleared, however. the internal logic circuit operates even when the pin is at a high level. the signal supplied to this pin is not synchronized with the clock. receives the supply voltage for both the logic circuit and driver. 5 0.5 v/3.3 0.3 v reference voltage for the ls1 and ls2 level shifters. must be connected to the system ground. v ee1 (for the driver) v ee2 (for the logic circuit)
m pd16650 5 cautions for use 1) power-on sequence to prevent latch-up disruption, the power must be switched on in the order: v cc ? v ee1 ? v ee2 ? v dd ? logic input when witching off, reverse the order. this order must be observed also during transition. 2) insertion of bypass capacitors the internal logic circuit operates at a high voltage. to make v ih and v il immune to noise, use capacitors of 0.1 m f or so between supply voltages as shown below. v dd v cc v ss v ee2 0.1 f m 0.1 f m 0.1 f m 3) negative voltage level shift if it is necessary to shift the level of a negative supply voltage, shift the v ee1 (driver supply voltage) level. the shift should be limited to within: v ee2 v ee1 v ee2 + 10 v note that shifting the v ee1 level results in the on-state output resistance and output fall time ratings being changed. 4) handling the v ee1 and v ee2 driver negative supply voltage pins for applications in which a negative supply voltage level is not shifted, connect the v ee1 pin (driver supply voltage) to the v ee2 pin (logic supply voltage) outside the tcp. fix all unused input pins to the v ee2 level.
m pd16650 6 timing chart (mc = v ss , 128-output mode, and r/l = v cc ) x 1 at the next stage x 2 at the next sta g e stvl (stvr) x 128 x 127 x 3 x 2 x 1 stvr (stvl) f x 1 2 3 127 128 129 130 caution do not change all outputs simultaneously, because such a sequence may result in malfunction.
m pd16650 7 timing chart (mc = v cc , 120-output mode, and r/l = v cc ) x 1 at the next stage x 2 at the next sta g e stvl (stvr) x 128 x 127 x 3 x 2 x 1 stvr (stvl) f x 1 2 3 119 120 121 122 cautions 1. do not change all outputs simultaneously, because such a sequence may result in malfunc- tion. 2. the output sequence in the 120-output mode is as follows: stvr (stvl) ? x 1 ? x 2 ... x 60 ? x 69 ... x 127 ? x 128 ? stvl (stvr)
m pd16650 8 absolute maximum ratings (t a = 25 c, v ss = 0 v) C0.5 to +28 C0.5 to +7 C0.5 to +42 C22 to +0.5 v ee2 C 0.5 to v dd2 + 0.5 10 10 C20 to +85 C55 to +125 recommended operating ranges (t a = C20 c to +70 c, v ss = 0 v) supply voltage supply voltage supply voltage supply voltage input voltage input current output current operating temperature range storage temperature range parameter symbol conditions v dd v cc v dd -v ee1 v dd -v ee2 v ee1 , v ee2 v i i i i o t a t stg. rated value v v v v v ma ma c c unit remark when shifting the level of v ee1 (driver supply voltage), satisfy the condition: v ee2 v ee1 v ee2 + 10 v note that shifting the v ee1 level results in the on-state output resistance and output fall time ratings being changed. electrical characteristics (t a = C20 c to +70 c, v dd = 20 v, v ee1 = v ee2 = C20 v, v cc = 3.3 0.3 v or 5.0 0.5 v, v ss = 0 v) parameter supply voltage supply voltage supply voltage supply voltage supply voltage supply voltage symbol conditions min. typ. max. unit v dd v ee1 v ee2 v dd -v ee1 v dd -v ee2 v cc v cc for the 3.3 v logic input for the 5.0 v logic input 16 v ee2 C20 20 3.0 4.5 3.3 5.0 25 v ee2 + 10 0 40 3.6 5.5 v v v v v v parameter input high voltage input low voltage output high voltage output low voltage output high current output low current on-state output resistance input leakage current dynamic drain current conditions min. typ. max. unit other than v cha other than v cha stvr(stvl), i oh = C40 m a stvr(stvl), i ol = 40 m a x n , v x = v dd C 1 v x n , v x = v ee1 + 1 v v x = v ee1 + 1 v or v dd C 1 v v 1 = 0 v, 5.0 v, or 3.3 v v dd , f f x = 31.5 khz v ee1/2 , f f x = 31.5 khz v cc , f f x = 31.5 khz 0.7v cc v ee2 v cc C 0.4 v ss 1.5 0.5 C0.5 50 v cc 0.3v cc v cc v ss + 0.4 C1.5 660 1.0 1.0 C1.0 100 v v v v ma ma w m a ma ma m a v ih v il v oh v ol i xoh i xol r on1 i il i dd i ee i cc symbol
m pd16650 9 switching characteristics (t a = C20 c to +70 c, v dd = 20 v, v ee1 = v ee2 = C20 v, v ss = 0 v, v cc = 3.3 0.3 v or 5.0 0.5 v) parameter stvr and stvl output delay driver output delay output rise time output fall time input capacitance maximum clock frequency conditions min. typ. max. unit c l = 20 pf clk ? stvr(stvl) c l = 220 pf clk ? x n c l = 220 pf, oe: l ? h c l = 220 pf, oe: h ? l c l = 220 pf c l = 220 pf t a = 25 c for cascade connection 100 600 600 700 700 700 700 300 300 15 ns ns ns ns ns ns ns ns pf khz t phl1 t plh1 t phl2 t plh2 t d1 t d2 t thl t tlh c i f f x symbol timing requirements (t a = C20 c to +70 c, v dd = 20 v, v ee1 = v ee2 = C20 v, v ss = 0 v, v cc = 3.3 0.3 v or 5.0 0.5 v) remark the logic input rise time (t r ) and fall time (t f ) must be within 20 ns (between 10 % and 90 % of the peak amplitude of the input). parameter clock pulse high width clock pulse low width data setup time data hold time conditions min. typ. max. unit 500 500 100 100 ns ns ns ns symbol pw f x (h) pw f x (l) t setup t hold duty = 50 % duty = 50 % stvr(stvl) ? clk clk ? stvr(stvl) ?
m pd16650 10 switching characteristic waveform (r/l = high) 1/f x pw x pw x x 50 % 50 % 50 % t setup t hold t phl2 t plh2 90 % 50 % 10 % 90 % 50 % 10 % t tlh t plh1 t thl t phl1 50 % stvl (stvr) 50 % 50 % t d1 50 % 50 % x n x n oe x n 50 % v cc v ss v cc v ss v oh v ol v cc v ss t d2 50 % f f f f
m pd16650 11 recommended mounting conditions when mounting this product, please make sure that the following recommended conditions are satisfied. for packaging methods and conditions other than those recommended below, please contact nec sales personnel. m pd16650n- mounting condition mounting method thermocompression soldering acf (sheet-shape bonding agent) caution to find out the detailed conditions for packaging the acf part, please contact the acf manufacturing company. be sure to avoid using two or more packaging methods at a time. reference nec semiconductor device reliability/quality control system (iei-1212) quality grades to necs semiconductor devices (iei-1209) condition heating tool 300 to 350 ?c; heating for 2 to 3 seconds; pressure 100 g (per solder) temporary bonding 70 to 100 ?c; pressure 3 to 8 kg/cm 2 ; time 3 to 5 secs. real bonding 165 to 180 ?c; pressure 25 to 45 kg/cm 2 ; time 30 to 40 secs. (when using the anisotropic conductive film sumizac1003 of sumitomo bakelite, ltd.)
m pd16650 [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11

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